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FPGA Verification Engineer - System Verilog/UVM (5-7 yrs) Bangalore (Semiconductor/VLSI/EDA)"},{"__CLASS__":"Adzuna::API::Response::Job Job at Adzuna.com


Skill Req (Mandatory) : - FPGA Verification experience (4-5 yrs min) - System Verilog (SV) - UVMF - High DO-254 proficiency - Other Communication Protocols - PCIe, CAN, Ethernet, SPI, UART, RS485 - Functional/Timing Simulation, Code Coverage Skill Req (Preferred) : - SVN or other Configuration tools usage - PCIe - DOORS and Synergy - TCL/TK scripting - Board level testing (ref:hirist.com)
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